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ASIC and FPGA Verification
Richard MundenData & ITRichard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints an...
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| ISBN | 9780125105811 |
| Språk | sv |
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Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints an...